The present invention relates to analog-to-digital converters (ADCs) and, more particularly, to sub-ranging successive approximation register (SAR) ADCs that combine a coarse flash ADC for the most-significant bits (MSBs) of the digital output and a fine SAR ADC for the least-significant bits (LSBs) of the digital output.
A multi-bit ADC generates a multi-bit digital output signal that corresponds to an applied analog input signal. A SAR ADC is a particular type of ADC that successively generates the digital output signal one bit at a time from the MSB down to the LSB. At each successive approximation, the SAR ADC uses a digital-to-analog converter (DAC) to generate a current intermediate analog approximation signal using the previously determined bits and a value of 1 for the current bit being resolved (with the rest of the bits set to 0), where the current approximation signal is compared to the analog input signal to determine whether the current bit should be a 1 or a 0. If the current approximation signal is greater than the analog input signal, then the current bit being resolved should be a 0; otherwise, the current bit being resolved should be a 1. U.S. Patent Application Publication No. 2012/0146822 A1, the teachings of which are incorporated herein by reference in their entirety, describes such a SAR ADC.
Y. Z. Lin et al., “A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS,” IEEE Transactions on Circuits and Systems-1: Regular Papers, Vol. 60, No. 3, March 2013, the teachings of which are incorporated herein by reference in their entirety, describe a 9-bit sub-ranging SAR ADC that combines a 3.5-bit coarse flash ADC and a 6-bit fine SAR ADC. The 3.5-bit flash ADC uses a “thermometer”-type resistor ladder to generate, in a single conversion step, a 14-bit thermometer value and a corresponding 4-bit binary value corresponding to the MSBs of the 9-bit digital output. The 4-bit value is then applied to a differential segmented capacitive DAC to generate an analog residue signal that is applied as the initial approximation signal to the 6-bit SAR ADC, which successively generates the bits of a 6-bit value corresponding to the LSBs of the 9-bit digital output, where the 4-bit value from the flash ADC overlaps the 6-bit value from the SAR ADC by one bit. These two digital values are then combined to form the 9-bit digital output value.
It is known in the art of SAR ADCs that a meta-stability condition can exist when the current approximation signal is sufficiently close to the analog input signal. In that case, the SAR ADC may mistakenly determine that the current bit has a value of 1, when it should have a value of 0, or vice versa. U.S. Pat. Nos. 8,482,449 B1; 8,872,691 B1; and 8,957,802 B1, the teachings of all of which are incorporated herein by reference in their entirety, describe techniques for detecting and correcting meta-stability conditions in SAR ADCs.
In a sub-ranging SAR ADC, such as the sub-ranging SAR ADC described by Y. Z. Lin et al., it is also possible for a meta-stability condition to exist in the coarse flash ADC. In particular, if the analog input signal is sufficiently close to one of the reference voltages generated by the resistor ladder of the flash ADC, then a meta-stability condition can exist in the coarse flash ADC, where the LSB of the multi-bit binary value generated by the flash ADC will have the wrong value. For the 9-bit sub-ranging SAR ADC of Y. Z. Lin et al., such a meta-stability condition could cause one of the 14 thermometric output bits generated by the resistor ladder of the 3.5-bit flash ADC to have an undetermined voltage level which may be neither logic level 0 nor logic level 1.
It would be advantageous to be able to detect and correct meta-stability conditions in a flash ADC of a sub-ranging SAR ADC.